The present invention generally relates to a multiphase clock generator and a selector circuit, and more particularly relates to a multiphase clock generator and selector circuit effectively applicable to a circuit that deals with multiple discrete frequencies in a wide range.
Where a high-speed serial data transmitter, complying with the IEEE 1394.b, for example, is made up of CMOS devices, a group of clock signals in multiple different phases some-times needs to be generated to lower the operating frequencies of the respective CMOS devices. A group of clock signals in multiple different phases will be herein called a xe2x80x9cmultiphase clockxe2x80x9d collectively. For example, a xe2x80x9c10-phase clockxe2x80x9d means a group of ten clock signals in mutually different phases. Specifically, ten 100 MHz clock signals, each having its phase shifted from the previous one by 10 ns, are generated instead of a single 1 GHz clock signal so that the respective CMOS devices can operate in parallel to each other responsive to this 10-phase clock. In this manner, the operating frequency of each CMOS device can be lowered and a high-speed data transmitter is implementable as a set of CMOS devices. Normally, a multiphase clock like this is generated using a PLL circuit.
As shown in FIG. 31, the loop of a PLL circuit includes a programmable frequency divider PD that can change its frequency division ratio. Using this programmable frequency divider PD, the PLL circuit changes the frequency division ratio and thereby changes the oscillation frequency of its voltage-controlled oscillator VCO. In this manner, a multiphase clock, consisting of ten clock signals PHB1 through PHB10 in various combinations, can be generated.
However, an IEEE 1394.b-compliant high-speed serial data transmitter has operating frequencies that cover a wide range, i.e., 125 Mbps, 250 Mbps, 500 Mbps, 1 Gbps and 2 Gbps. Accordingly, where the multiphase clock generator such as that illustrated in FIG. 31 is applied to such a high-speed serial data transmitter, its VCO must also operate in that wide range correspondingly. For that reason, it is difficult to finely tune the VCO.
It is true that the operating frequencies of an IEEE 1394.b-compliant high-speed serial data transmitter cover a wide range. But those operating frequencies can be nothing but discrete ones. FIG. 32 illustrates a multiphase clock generator utilizing this feature. In the multiphase clock generator shown in FIG. 32, the VCO is made to oscillate at a constant frequency but the frequency is changed using an external frequency divider DIV. Also, in this circuit, each of the ten clock signals PHA1 through PHA10 output from the VCO as a 10-phase clock has its frequency divided by associated one of the ten D-flip-flops DFF included in the frequency divider DIV. Accordingly, there is no need to tune the VCO but just the frequency division ratio of the D-flip-flops DFF should be changed to obtain a 10-phase clock consisting of clock signals PHC1 through PHC10 with a desired frequency.
In the multiphase clock generator shown in FIG. 32, however, the phase difference between two consecutive clock signals of the 10-phase clock PHA1 through PHA10 output from the VCO is equal to the difference between two consecutive ones of the 10-phase clock PHC1 through PHC10 output from the frequency divider DIV. For example, suppose the 10-phase clock PHA1 through PHA10 has a phase difference of 1 ns and a frequency of 100 MHz. In that case, the 10-phase clock PHC1 through PHC10 with a frequency of 50 MHz has waveforms as shown in FIG. 33. Referring to FIG. 33, the phase difference of the 10-phase clock PHC1 through PHC10 is also 1 ns, which is equal to that of the 10-phase clock PHA1 through PHA10.
Accordingly, the multiphase clock generator shown in FIG. 32 cannot obtain a multiphase clock PHC1 through PHC10 having a desired phase difference.
It is therefore an object of the present invention to provide a multiphase clock generator that can obtain a multiphase clock having a desired frequency and a desired phase difference.
A multiphase clock generator according to an aspect of the present invention includes oscillator, first selecting means and frequency dividing means. The oscillator generates a first multiphase clock having a predetermined frequency and including a number of clock signals. In the first multiphase clock, the phase of each clock signal is shifted from that of the previous one by a first phase difference. The first selecting means receives the first multiphase clock from the oscillator and outputs a second multiphase clock including the same or a different number of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency dividing means receives the second multiphase clock from the first selecting means, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.
In the inventive multiphase clock generator, the phase difference of the third multiphase clock is equal to that of the second multiphase clock output from the first selecting means. In other words, the phase difference of the third multiphase clock is determined by the first selecting means. Accordingly, by adjusting the integer n to be multiplied together with the first phase difference by the first selecting means, the third multiphase clock can have a desired phase difference. For that reason, no fine adjustment is needed for the oscillator.
Also, the frequency of the third multiphase clock is obtained by having the predetermined frequency of the first multiphase clock divided by the frequency dividing means at a certain ratio. Accordingly, by adjusting the frequency division ratio of the frequency dividing means, the third multiphase clock can have a desired frequency.
In one embodiment of the present invention, the frequency dividing means preferably includes a plurality of frequency dividing units. A first one of the units is associated with a first one of the clock signals included in the second multiphase clock received from the first selecting means. And the first unit preferably divides the frequency of the first clock signal by the predetermined number after a second one of the units, which is associated with a second one of the clock signals that has a phase lead over the first clock signal by the second phase difference, has started to divide the frequency of the second clock signal.
In such an embodiment, even if one of the clock signals in the second multiphase clock output from the first selecting means is in phase with another one of the clock signals, it is possible to prevent two frequency dividing units, associated with these clock signals, from starting the frequency division at the same time.
In this particular embodiment, each said frequency dividing unit preferably includes a single- or multi-stage flip-flop and inverting means. The flip-flop preferably includes a clock terminal, at which an associated one of the clock signals is received. The inverting means preferably inverts an output at a last stage of the flip-flop and then supplies the inverted output to an input terminal at an initial stage of the flip-flop. And the inverting means of the first unit is activated when an output at a last stage of a flip-flop, included in the second unit associated with the second clock signal, changes. The second clock signal has the phase lead over the first clock signal, associated with the first unit, by the second phase difference.
In such an embodiment, while the last-stage output of the flip-flop in the second unit does not change, the inverting means of the first unit is deactivated and the initial-stage input of the flip-flop in the first unit has a fixed value. Accordingly, the last-stage output of the flip-flop in the first unit also has a fixed value. And it is not until the last-stage output of the flip-flop in the second unit changes that the inverting means of the first unit is activated. When the inverting means of the first unit is activated, an inverted version of the last-stage output of the flip-flop in the first unit is supplied to the initial-stage input terminal of the flip-flop in the first unit. As a result, the first unit starts to divide the frequency.
In another embodiment of the present invention, the first selecting means preferably changes the integer n responsive to an external signal.
In still another embodiment, the frequency dividing means preferably divides the frequency of the second multiphase clock, received from the first selecting means, at a ratio corresponding to an external signal.
In yet another embodiment, the multiphase clock generator preferably further includes clock synthesizing means for generating a serial clock signal from the third multiphase clock that has been received from the frequency dividing means.
In this particular embodiment, the clock synthesizing means preferably includes a first type of logic circuits and a second type of logic circuit. Each said logic circuit of the first type generates a pulse signal from an associated one of the clock signals included in the third multiphase clock received from the frequency dividing means and an inverted version of another one of the clock signals that has a phase shifted from the associated clock signal by the second phase difference. The pulse signal has a pulse width equal to the second phase difference and also has a period equal to that of the third multiphase clock. The second type of logic circuit synthesizes the pulse signals output from the logic circuits of the first type.
A multiphase clock generator according to this embodiment can obtain the third multiphase clock and a serial clock signal. Accordingly, where a block for performing parallel processing using a multiphase clock and a block for performing serial processing using a serial clock signal coexist on the same LSI chip, the clock generator can supply both the multiphase clock and serial clock signal. Normally, a circuit for generating a serial clock signal should be provided separately in such a case, and the serial clock generator separately provided needs an internal PLL. In contrast, the clock synthesizing means of the present invention needs no PLL. As a result, the chip area occupied can be saved and the cost can be cut down eventually.
In this particular embodiment, the clock synthesizing means preferably further includes second selecting means. The second selecting means supplies first and second clock signals to each of the logic circuits of the first type. The first clock signal is one of the clock signals, which is included in the third multiphase clock received from the frequency dividing means and which is associated with the logic circuit of the first type. The second clock signal is complementary to a clock signal that has a phase shifted from the first clock signal by the second phase difference. And each said logic circuit of the first type preferably generates the pulse signal responsive to the first and second clock signals supplied from the second selecting means.
In such an embodiment, a delay caused on a path through which the first clock signal is supplied to one of the logic circuits of the first type is no different from a delay caused on a path through which the second clock signal is supplied to the logic circuit. As a result, a serial clock signal with a 50xe2x80x9450 duty can be obtained.
A selector circuit according to another aspect of the present invention receives a first multiphase clock and outputs a second multiphase clock. The first multiphase clock has a predetermined frequency and includes a number of clock signals. In the first multiphase clock, the phase of each clock signal is shifted from that of the previous one by a first phase difference. The second multiphase clock includes the same or a different number of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer.
In one embodiment of the present invention, the selector circuit changes the integer n responsive to an external signal.